The following waveforms show the behavior of scfifo megafunction for the chosen set of parameters in design lpm_fifo0.v. The design lpm_fifo0.v has a depth of 64 words of 18 bits each. The output of the fifo is unregistered. The fifo is in legacy synchronous mode. The data becomes available after 'rdreq' is asserted; 'rdreq' acts as a read request.
The above waveform shows the behavior of the design under normal read and write conditions with aclr .
The above waveform shows the behavior of the design for FIFO full condition. In the example above, data is written into the FIFO till it is full, then data is read back.